1. Field of the Invention
The present invention relates to a method for monitoring an internal signal for controlling the operation of a sense amplifier of a memory device and an apparatus therefor, and more particularly to a method for monitoring an internal signal for controlling the operation of a sense amplifier of a memory device and an apparatus therefor that can control the operation section of the sense amplifier in accordance with a variation of the operating frequency of the memory device.
2. Description of the Prior Art
FIG. 1 is a view explaining read/write operations of a general memory device.
As illustrated in FIG. 1, in a write operation, data applied through an input/output (I/O) data pad is transferred to a bit-line sense amplifier through a data input buffer, a data input register, and a data driver. In a read operation, cell data amplified by the bit-line sense amplifier is transferred to the I/O data pad through a data sense amplifier, a pipe register, and a data output buffer.
In FIG. 1, a Signal Yi is a pulse signal for controlling column lines, which controls the operation of a data bus connecting the bit-line sense amplifier and the data sense amplifier. While the Signal Yi for controlling the data bus is enabled, write data is transferred from a write driver to the bit-line sense amplifier, and read data is transferred from the bit-line sense amplifier to the data sense amplifier.
Accordingly, in order to transfer valid data in an active operation (i.e., in a read or write operation), it is favorable to widen the pulse width of the Signal Yi. The wide pulse width of the Signal Yi heightens the data restore under the condition of the same tDPL (which is a time period from the time point that a CAS (Column Address Strobe) pulse signal is internally generated by a write command to the time point that a pre-charge pulse signal is internally generated by a pre-charge command).
Accordingly, it is general to first set the pulse width of the Signal Yi as wide as possible within a permitted limit and then to reduce the pulse width as needed. For reference, as the operating frequency of the memory device is increased (i.e., as the clock period is reduced), the permitted pulse width of the Signal Yi becomes reduced.
Meanwhile, the Signal Yi as described above is made by receiving a read/write strobe pulse signal rdwtstbzpl3 output from a read/write strobe pulse generating circuit, and thus the read/write strobe pulse generating circuit will be explained hereinafter.
FIG. 2a is a circuit diagram of a conventional read/write strobe pulse generating circuit, and FIG. 2b is a waveform diagram of signals appearing in the circuit of FIG. 2a. 
Referring to FIG. 2a, a pulse signal extyp8 and a pulse signal icasp6 are signals for making data transmission lines of a memory cell array and data transmission lines of a peripheral circuit short or open in order to read and provide data stored in the cell array (i.e., core region) of the memory device to the peripheral circuit or to write data applied to the peripheral circuit in the memory cell array. For convenience in explanation, the region that includes the memory cell and the bit-line sense amplifier is called a core region, and the remaining region is called a peripheral circuit.
More specifically, the extyp8 signal is a pulse signal generated in synchronization with a clock signal if a read or write command (i.e., burst command) is applied from an outside. The icasp6 signal is a signal used to operate the memory device by creating a self burst operation command as long as a burst length determined by an MRS (Mode Register Set) from a clock that is one-period later than a clock at which the read or write command is applied from the outside.
The read/write strobe pulse signal rdwtstbzpl3 is a signal that is activated in synchronization with burst operation commands (External=extyp8 & Internal=icasp61) whenever these signals are activated and as long as the burst length determined by the general MRS. That is, the rdwtstbzp13 signal is a signal that reports the time point of activation of an input/output sense amplifier used to sufficiently amplify data transmitted from the core region to the peripheral circuit and to transmit the amplified data to a data output buffer. After the data is amplified and transmitted, the rdwtstbzp13 signal is used to reset the data transmission lines of the peripheral circuit.
A pwrup signal is a signal for setting an initial value, which is first in a high level, goes to a low level, and then is kept in the low level. A term_z signal is a signal used in a test mode, and is kept in a low level during its normal operation. A tm_clkpulsez signal is a signal used in a test mode. The signals as described above will be explained in more detail later.
The operation of the circuit illustrated in FIG. 2a will now be explained with reference to a waveform diagram of FIG. 2b. 
As can be seen in FIG. 2b, if a read/write command is applied in synchronization with a clock signal, a pulse signal extyp8 is generated. If the extyp8 signal is generated, plural pulses icasp6 are sequentially generated in synchronization with the next clock. As illustrated in FIG. 2b, the read/write strobe pulse signal rdwtstbzp13 is generated in synchronization with a rising edge of the pulse signals extyp8 and icasp6.
It can be seen from the conventional circuit of FIG. 2a that a pulse width adjustment unit 200 for determining the pulse width of the read/write strobe pulse signal rdwtstbzp13 is fixed irrespective of the operating frequency of the memory device. That is, because a delay time obtained through a delay unit 20 of the pulse width adjustment unit 200 is fixed, the pulse width of the signal output from the pulse width adjustment unit 200 is just constant.
If the operating frequency of the memory device is varied, however, it becomes necessary to adjust the pulse width of the read/write strobe pulse signal rdwtstbzpl3.
Conventionally, if the operating frequency of the memory device is varied, the delay time of the delay unit 20 is adjusted by correcting a metal option during a FIB work. However, this requires plenty of cost and time.
The conventional circuit also has the problems in that it is not easy to monitor the internal voltage of the memory device after a packaging process of the memory device.